1. Field of the Invention
The present invention relates to a magneto-resistive random access memory and a method of manufacturing the same. More particularly, the present invention relates to a magneto-resistive random access memory having a tunneling junction and a method of manufacturing the same.
2. Description of the Related Art
Magneto-resistive random access memories (RAMs) are formed of metal oxide semiconductor (MOS) transistors and magnetic tunneling junctions which are electrically connected to the MOS transistors to serve as signal storing capacitors. Thus, recorded data can be read via the magnetic tunneling junctions by applying a predetermined voltage to the MOS transistors.
A magneto-resistive RAM has the advantages of speed and non-volatility, making it very suitable for use as a memory device. Also, a magneto-resistive RAM has a cell structure that allows structures of peripheral circuits to be simplified.
Magneto-resistive RAMs generally use a memory core that connects MOS transistors and magnetic tunneling junction devices in series. Here, a data storage device must have a resistance value greater than that of a MOS transistor operating as a simple switch. Thus, magnetic tunneling junctions are currently used as memory devices of magneto-resistive RAMs.
Currently used magnetic tunneling junctions include an oxide aluminum layer (Al2O3) as an oxide barrier. The oxide aluminum layer (Al2O3) is formed by depositing and then oxidizing an aluminum (Al) layer. The oxide barrier serves as a potential barrier in the magnetic tunneling junction.
However, a potential barrier formed by such an oxide layer barrier is not refined, and thus a magnetic resistance ratio (hereinafter referred to as a MR ratio) tends to be reduced by an amount inversely proportional to an applied voltage. The reduction in the MR ratio may cause an operation error when storing and reading data, thereby greatly deteriorating the reliability of such a memory device.
In an effort to solve the problems described above, it is a feature of an embodiment of the present invention to provide a magneto-resistive random access memory that enables a potential barrier of a magnetic tunneling junction to be stably maintained so that a MR ratio may be stabilized and a reduction in the MR ratio with respect to an applied voltage may be minimized, and a manufacturing method thereof.
Accordingly, to achieve a feature of an embodiment of the present invention, there is provided a magneto-resistive random access memory including a MOS transistor formed of a first gate, a source junction and a drain junction on a semiconductor substrate, a lower electrode connected to the source junction, a first magnetic layer formed on the lower electrode, a dielectric barrier layer including at least aluminum and hafnium on the first magnetic layer which, together with the first magnetic layer, forms a potential well, a second magnetic layer formed on the dielectric barrier layer to be opposite the first magnetic layer, an upper electrode formed on the second magnetic layer, a second gate interposed between the first gate and the lower electrode to control the magnetic data of one of the first and second magnetic layers, and a bit line positioned orthogonal to the first gate and electrically connected to the upper electrode.
Preferably, the lower electrode includes a lower electrode layer formed to electrically connect the semiconductor substrate, and a buffer layer formed of an anti-magnetic material on the lower electrode layer. The lower electrode layer may be formed of a metal, such as aluminum (Al), ruthenium (Ru), tantalum (Ta), copper (Cu) or an alloy of Al and Cu. It is preferable that a barrier layer formed of one of an aluminum nitride (AlN) layer, a titanium nitride (TiN) layer, and a tungsten nitride (WN) layer is further formed under the lower electrode layer to intercept impurity atoms. Also, the buffer layer may be formed of tantalum (Ta), ruthenium (Ru), or the like. Alternatively, the buffer layer may be formed of one of IrMn, PtMn and FeMn. The first magnetic layer (generally, called a pinned layer) may be formed of CoFe, Co or NiCoFe. It is preferable that the dielectric barrier layer is formed of an alloy oxide layer in which hafnium is added to an aluminum oxide layer (Al2O3).
The second magnetic layer, which is a free layer film, may be formed of a ferromagnetic material on the dielectric barrier layer. The second magnetic layer may be formed of a paramagnetic material, preferably Permalloy (Py(NiFe)). The upper electrode is preferably formed of at least one of Al, Ru and Ta.
To provide another feature of an embodiment of the present invention, a method of manufacturing a magneto-resistive random access memory is provided, the method including forming an isolation dielectric layer on a semiconductor substrate to form a device active region, forming a first gate, a source area and a drain area in the device active region to form a MOS transistor, forming a second gate parallel to the first gate and forming a lower electrode of a conductive material to be connected to the source area of the MOS transistor, forming a first magnetic layer on the lower electrode to form a predetermined magnetic domain, forming a dielectric barrier layer of at least hafnium (Hf) and aluminum (Al) on the first magnetic layer, forming a second magnetic layer opposite the first magnetic layer on the barrier layer, and forming an upper electrode on the second magnetic layer so that the upper electrode is electrically connected to the second magnetic layer.
It is preferable that the isolation dielectric layer is formed of an oxide layer.
In the method described above, forming the first gate preferably includes forming a thin gate dielectric layer in the device active region, sequentially forming on the gate dielectric layer a gate conductive layer and a capping insulating layer that acts as a mask, forming a first gate pattern by in the capping insulating layer acting as a mask and the gate conductive layer, forming source and drain junctions on both sides of the first gate to complete a MOS transistor.
The gate dielectric layer may be formed of an oxide layer. Also, sidewall spacers may be formed of a dielectric material on sidewalls of the first gate pattern.
It is preferable that the gate conductive layer is formed of doped polycrystalline silicon. It is also preferable that the gate conductive layer be deposited by chemical vapor deposition. It is preferable that the capping insulating layer acting as a mask is a silicon dielectric layer formed by chemical vapor deposition. It is also preferable that the source and drain junctions be formed by an ion implantation method.
In the method described above, forming the second gate and the lower electrode preferably include forming a first interlayer insulating film on the entire surface of the semiconductor substrate, forming a first gate on the first interlayer insulating film, forming a second interlayer insulating film on the entire surface of the semiconductor substrate, forming a lower electrode layer of a conductive material layer on the second interlayer insulating film, forming a buffer layer of an anti-magnetic material on the lower electrode layer, and forming a lower electrode pattern on the lower electrode layer and the buffer layer.
Preferably, the conductive material layer is formed of at least one of Al, Ta, Ru, and AlN. The buffer layer may be formed of one of tantalum (Ta) or ruthenium (Ru) to improve surface flatness. However, the buffer layer may be formed of IrMn, PtMn, or FeMn. The first magnetic layer (pinned layer) may be formed of a ferrimagnetic material. Preferably, the first magnetic layer is formed of one of CoFe, Co, or NiCoFe.
In the method described above, forming the barrier layer preferably includes forming an aluminum-hafnium-oxide layer on the first magnetic layer by forming a multi-layered film of aluminum/hafnium on the first magnetic layer, supplying an oxygen source into the multi-layered film, and performing a thermal treatment to oxidize the aluminum and the hafnium. Here, the multi-layer is preferably formed by a physical vapor deposition method such as metal sputtering.
In the method described above, the second magnetic layer (free layer film), is preferably formed of a paramagnetic material (Py(NiFe)), which is a ferromagnetic material.
In the method described above, forming the upper electrode preferably includes forming a metal layer for an upper electrode layer on the second magnetic layer, and patterning the upper electrode layer to form an upper electrode. Here, the metal layer is preferably formed by depositing an aluminum nitride layer (AlN), on a metal layer formed of aluminum (Al), ruthenium (Ru), or tantalum (Ta).
After patterning the upper electrode, in order to secure the area of the magnetic memory device, the metal layer, the second magnetic layer, the barrier layer, and the first magnetic layer are removed by a general etching process, to complete the magnetic memory device.